Computer-aided modeling and evaluation of reconfigurable VLSI processor arrays with VHDL

In this paper, we present an integrated computeraided design environment, the VAR (VHDL-based Array Reconfiguration) system, for the tasks of design, reconfiguration, simulation, and evaluation in an architecture modeled by VHDL. An easily diagnosable and reconfigurable two-dimensional defect-tolerant PE-switch lattice array is used as an example to illustrate the methodology of VAR. VAR allows the designers study and evaluate fault diagnosis and reconfiguration algorithms by inserting faults, which are generated based on manufacturing yield data, into the array and then locating the faulty PE’s as well as simulating the reconfiguration process. Thus, VAR can assist the designers in evaluating different combinations of fault patterns, fault diagnosis algorithms, reconfiguration algorithms, and reconfigurable architectures through a complete set of figures of merit which aim at architectural improvements. Extensive simulation and evaluation have been performed to demonstrate and support the effectiveness of VAR. The results from this research can drive the applications of large-area VLSI or WSI (wafer scale integration) closer to reality and result in low-cost, high-yield array architectures.